IEEE

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k ...
IEEE

Metal-Assisted Chemical Etching Toward Scallop-Free-Sidewall Through-Silicon Vias: A Review

Abstract: With recent advancement and progress in the field of 3-D integration for modern high-speed and high-bandwidth electronic systems, there is an ever-increasing demand for high-quality ...