IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
IEEE

Tutorial: Analog Circuit Design in Bipolar-CMOS-DMOS (BCD) Technologies

Abstract: Bipolar-CMOS-DMOS (BCD) technologies enable applications of high industrial interest, whereby high-voltage and highpower circuits are combined with high-density digital logic on a single die ...
Electronic Design

Alternating Control and Optimizing Bandwidth in Buck-Boost Circuits

H-bridge buck-boost ICs are widely used in applications requiring a constant voltage or current source even when the system battery drops to lower voltages. They make sense when a single-stage ...
Electronic Design

Creating On-Chip MEMS Sensors in CMOS

Nanusens' novel approach to creating nanoscale sensor structures inside the CMOS layers. How the methodology helps shrink cost and size. Previously, MEMS sensors were created by employing proprietary ...